All of the standard FPGA VI debugging techniques used to simulate an FPGA (execution highlighting, probes, and sampling probes) may be used on the FPGA VI block diagram while the PC VI executes.Similar concept as programmatic front-panel communication in which the PC VI operates the FPGA front-panel controls and reads its indicators.The “Desktop Execution” node (DEN) connects to any or all of the FPGA I/O nodes when the FPGA target is in simulation mode.Interactively write and read FPGA I/O lines from the PC VI front panel.Apply a known sequence to the FPGA inputs and check whether the FPGA produces the correct output sequence.Implement a testbench with the FPGA VI as the “device under test” and the PC VI emulates the external environment of the FPGA, acting as the test pattern generator and monitor.Develop and debug an FPGA VI by applying test patterns to the FPGA inputs and observing the resulting FPGA outputs.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |